Lef def files

Because nonorthogonal segments are not allowed, subsequent points in a connected sequence must create orthogonal paths. For example, the following sequence is a valid path:.

The following sequence is not valid because it represents a nonorthogonal segment. Some technologies require larger widths for wrong-way routing than in the preferred direction. If the wrong-way width is larger than the default or NDR width, then the wrong-way width is used for wrong-way routes on that layer.

The implicit routing extension is still half of the default or NDR width, even for wrong-way routes. Some older tools may not understand this behavior. If these tools check wrong-way width, then the DRC rules may flag false violations.

RC extraction that does not understand the wrong-way width will also be incorrect, although wrong-way routes are generally short and the width difference is small, so the RC error is normally negligible. These width rules are mutually exclusive, so only one of the 3 rules is allowed on one routing layer.

Example Impact of default and nondefault rules on wrong-way segment. Rule width. Vertical Route Width. Vertical Route Extension. Horizontal Route Width. Horizontal Route Extension. Figure Default rule on wrong way segment. Figure Non-Default rule on wrong way segment. If you specify the pin's placement status, you must specify its location and orientation. Example Shielded Net. NETS 1 ;. Defines any nondefault rules used in this design that are not specified in the LEF file.

This section can also contain the default rule and LEF nondefault rule definitions for reference. Every nondefault rule must specify a width for every layer. VIA viaName. Example Nondefault Rules. Defines external pins. Each pin definition assigns a pin name for the external pin and associates the pin name with a corresponding internal net name.

The pin name and the net name can be the same. When the design is a chip rather than a block, the PINS statement describes logical pins, without placement or physical information. Example Antenna Model Statement. PINS ;. Example Multi-Mask Patterns for Pins. The VIA1 via will have:. Figure Multi-Mask Patterns for Pins. Example Net Expression and Supply Sensitivity. The following PINS statement defines sensitivity and net expression values for five pins in the design myDesign :.

PINS 4 ;. Specifies the routing layer used for the pin, and the pin geometry on that layer. Specifies the layer and a sequence of at least three points to generate a polygon for this pin. Specifies the minimum spacing allowed between this pin and any other routing shape. This distance must be greater than or equal to minSpacing. Specifies that this pin has a width of effectiveWidth for the purpose of spacing calculations.

Example Port Example. Assume a block that is x database units with a 0,0 origin in the middle of the block. If you have the following pins defined, Figure illustrates how pin BUSA[0] is created for two different placement locations and orientations:.

PINS 2 ;. Figure Port Illustration. Example Port Statement With Polygon. The following PINS statement creates a polygon with a degree angle:. PINS 3 ;. Pin is used for connectivity to the chip-level ground distribution network. Pin is used for connectivity to the chip-level power distribution network.

In the design of place and route blocks, you sometimes want to add extra physical connection points to existing signal ports usually to enable the signal to be accessed from two sides of the block. One pin has the same name as the net it is connected to. Any other pins added to the net must use the following naming conventions. Example Pin Statements. The pin is first defined in Verilog for a chip-level design. PINS 5 ;. Example Pin Properties Statement. Lists all properties used in the design.

RANGE min max. Defines regions in the design. A region is a physical area to which you can assign a component or group. All instances assigned to this type of region must be exclusively placed inside the region boundaries.

No other instances are allowed inside this region. All instances assigned to this type of region should be placed inside this region; however, it is a preference, not a hard constraint. Other constraints, such as wire length and timing, can override this preference.

Example Regions Statement. Example Row Statements. Assume siteA is by database units. Defines scan chains in the design. Scan chains are a collection of cells that contain both scan-in and scan-out pins. IN pin. Specifies the scan-in pin. If you do not specify a scan-in pin, the router uses the pin you specified for the common scan pins.

OUT pin. Specifies the scan-out pin. If you do not specify a scan-out pin, the router uses the pin you specified for the common scan pins. BITS numBits. Specifies the sequential bit length of any chain element. This allows application tools that do not have library access to determine the sequential bit length contribution of any chain element to ensure the MAXBITS constraints are not violated for chains in a given partition.

You can specify 0 to indicate when elements are nonsequential. Default: 1 Type: Integer. Example Partition Scanchain. The maximum allowed bit length of the chain is assumed to be the sequential length of the longest chain in any clock1 partition. The specified maximum bit length for this chain is Example Scan Chain Statements. Nets ; Number of nets resulting after scan chain synthesis. Defines the rectangular shapes that form the slotting of the wires in the design.

Each slot is defined as an individual rectangle. Example Slots Statements. SLOTS 2 ;. SLOTS 1 ;. Defines netlist connectivity and special-routes for nets containing special pins. Special-routes are created by "special routers" or "manually", and should not be modified by a signal router. In case of conflicting values for an argument, the DEF reader uses the last value encountered for the argument. On output, the writer outputs the netlist in either format, depending on the command arguments of the output command.

Example Fixed Bump. The following example describes a logical pin that is connected to a bump and an input driver cell. The pin is assigned in the PIN statement. PINS NEW layerName routewidth. RECT layerName pt pt. Creates an array of power vias of the via specified with viaName. Do not specify 0 as a value. Type: Integer. For an example of a via array, see Example Type: Integer, specified in database units Default: 0. Specifies which mask for double or triple patterning lithography to use for the next wire.

Most applications support maskNum values of 0, 1, 2, or 3 only for double or triple patterning. For the cut-layer, the cutMaskNum variable will define the mask for the bottom-most, and then the left-most cut. The via-master must have a mask defined for all the cut shapes and every via-master cut mask is "shifted" from 1 to 2, and 2 to 1 for two mask layers, and from 1 to 2, 2 to 3, and 3 to 1 for three mask layers , so the lower-left cut matches the cutMaskNum value.

Example Via Arrays. Therefore, the following statement creates a metal1 wire of width 50 from to along with the via array that starts at There is no wire segment between 30 30 and 40 Represents a fill shape that does not require OPC. It is normally connected to a power or ground net. Floating fill shapes should be in the FILL section. Represents a fill shape that requires OPC. Figure Fill Shapes. VIA viaName [ orient ] pt Example Special Nets Statements. Signoff DRC tools may require metal shapes under the trim metal shapes to fill up the gaps between the line-end of wires sandwiched by the trim metal shape to be output in DEF.

As trim metal shapes need to be aligned and merged, dummy patches are often added even on OBS and unconnected pins. Routing points define the center line coordinates of a route. If a route has a degree edge, it has a width of routeWidth , and extends from one coordinate x y to the next coordinate. If either endpoint has an optional extension value extValue , the wire is extended by that amount past the endpoint.

Some applications convert the extension value to an equivalent route that has the x and y points already extended, with no extension value. If no extension value is defined, the wire extension is 0, and the wire is truncated at the endpoint. The routeWidth must be an even value to ensure that the corners of the route fall on a legal database coordinate without round off.

Because most vendors specify a manufacturing grid, routeWidth must be an even multiple of the manufacturing grid in order to be fabricated. The routeWidth must be an even multiple of the manufacturing grid in order to keep all of the coordinates of the resulting outer wire boundary on the manufacturing grid. No corrections, such as snapping to manufacturing grid, should be applied, and any extension values are ignored.

The routeWidth indicates the desired user width, and represents the minimum allowed width of the wire that results from the style when the degree edges are snapped to the manufacturing grid. Specifies the orientation of the site at that location.

Note: Legal placement locations for macros with site patterns must match the site pattern inside the macro to the site pattern in the design rows. Specifies the number of sites to add in the x and y directions. You must specify values that are greater than or equal to 0 zero. Specifies the spacing between sites in the x and y directions. Example Macro Site. The following statement defines a macro that uses the sites created in Example :.

END myTest. Figure illustrates the placement results of this definition. The following statement includes the gate-array site pattern syntax. It uses two F sites in a row with N North orientation.

This definition produces a cell with the sites shown in Figure Specifies a placement bounding rectangle, in microns, for the macro. The bounding rectangle always stretches from 0, 0 to the point defined by SIZE. The bounding rectangle width and height should be a multiple of the placement grid to allow for abutting cells.

For blocks, the placement bounding rectangle typically contains all pin and blockage geometries, but this is not required. For example, typical standard cells have pins that lie outside the bounding rectangle, such as power pins that are shared with cells in the next row above them. Specifies which macro orientations should be attempted by the placer before matching to the site of the underlying rows.

In general, most standard cell macros should have symmetry X Y. N North is always a legal candidate. For each type of symmetry defined, additional orientations become legal candidates. For more information on defining symmetry, see "Defining Symmetry". If you define a cover macro with its actual size, some place-and-route tools cannot place the rest of the cells in your design because it uses the cell boundary to check for overlaps.

You can resolve this in two ways:. Symmetry statements specify legal orientations for sites and macros. Figure illustrates the normal orientations for single-height, flipped and abutted rows with standard cells and sites. The following examples describe typical combinations of orientations for standard cells. Applications typically create only N or FS for flipped row orientations for horizontal standard cell rows; therefore, the examples describe these two rows.

Example Single-Height Cells. These symmetries work with flipped and abutted rows, as well as rows that are not flipped and abutted, so if the rows are all N orientation, the cells all have N or FN orientation. Example Double-Height Cells. Usually, double-height rows are just N orientation rows that are abutted and aligned with a pair of single-height flipped and abutted rows.

Example Special Orientations. Some single-height cells have special orientation needs. For example, the design requires flipped and abutted rows, but only N and FS orientations are allowed because of the special layout of well taps on the right side of a group of cells that borrow from the left side of the next cell.

That is, you cannot place an N and FN cell against each other in one row because only N cells are allowed in an N row. Example Vertical Rows. Vertical rows use N or FN row and site orientations. Otherwise, the meaning of the site symmetries and macro symmetries is the same as those for horizontal rows.

Single-height sites are normally given symmetry X , and single-height cells are normally given symmetry X Y. Specifies the effective design rule width. If specified, the obstruction or pin is treated as a shape of this width for all spacing checks. Indicates that the obstruction shapes block signal routing, but do not block power or ground routing. This can be used to block signal routes that might cause noise, but allow connections to power and ground pins.

The syntax for stepPattern is defined as follows:. Specifies the spacing, in distance units, between the columns and rows of points.

Note: For macro obstructions, you can specify cut, implant, or overlap layers. Specifies which mask from double- or triple-patterning to use for this shape. The maskNum variable must be a positive integer. Most applications only support values of 1, 2, or 3.

Shapes without any defined mask have no mask set they are considered uncolored. The uncolored PIN shapes can be assigned to an arbitrary mask as long as they do not have a spacing conflict with neighbor objects.

The meaning of uncolored OBS shapes depends on the cell. For other MACRO types, uncolored OBS shapes are assumed to be abstractions that may be any mask, so other shapes must be spaced far enough away to avoid a violation to any mask shape at that location. Specifies which mask for double- or triple-patterning lithography to be applied to via shapes on each layer. The viaMaskNum is a hex-encoded 3 digit value of the form:.

A value of 0 means the shape on that layer has no mask assignment is uncolored , so means the top layer is uncolored. If either the first or second digit is missing, they are assumed to be 0, so and 13 means the same thing.

Most applications only support maskNum values of 0, 1, 2, or 3 for double or triple patterning. The topMaskNum and bottomMaskNum variables specify which mask the corresponding metal shape belongs to. The via-master metal mask values have no effect.

For the cut-layer, the cutMaskNum defines the mask for the bottommost, and then the leftmost cut. For multi-cut vias, the via-instance cut masks are derived from the via-master cut mask values. The via-master must have a mask defined for all of the cut shapes and every via-master cut mask is "shifted" 1 to 2, 2 to 1 for two mask layers, and 1 to 2, 2 to 3, 3 to 1 for three mask layers so the lower-left cut matches the cutMaskNum value.

For multiple disjoint metal shapes, the via-instance metal masks are derived from the via-master metal mask values. Shapes without any defined mask that need to be assigned, can be assigned to an arbitrary choice of mask by applications. PATH pt. Creates a path between the specified points, such as pt1 pt2 pt3. The path automatically extends the length by half of the current width on both endpoints to form a rectangle. The line between each pair of points must be parallel to the x or y axis degree angles are not allowed.

You can also specify a path with a single coordinate, in which case a square whose side is equal to the current width is placed with its center at pt. Specifies a sequence of at least three points to generate a polygon geometry.

Every polygon edge must be parallel to the x or y axis, or at a degree angle. Each POLYGON statement defines a polygon generated by connecting each successive point, and then by connecting the first and last points. RECT pt pt. Specifies a rectangle, where the two points specified are opposite corners of the rectangle. Specifies the minimum spacing allowed between this particular OBS and any other shape. The minSpacing value overrides all other normal LAYER-based spacing rules, including wide-wire spacing rules, end-of-line rules, parallel run-length rules, etc.

This is sometimes needed for cells with large drive strengths to avoid electromigration problems by restricting the router to connect only to the middle of the output pin. Tools may change larger values to the maximum spacing value with a warning. VIA pt viaName. Specifies the width that the PATH statements use. If you do not specify width , the default width for that layer is used.

Example Layer Geometries. Example Layer Geometries - multi-mask patterns. Figure Via-master multi-mask patterns.

Defines a set of obstructions also called blockages on the macro. You specify obstruction geometries using the layer geometry syntax. See "Layer Geometries" for syntax information. Normally, obstructions block routing, except for when a pin port overlaps an obstruction a port geometry overrules an obstruction.

For example, you can define a large rectangle for a metal1 obstruction and have metal1 port in the middle of the obstruction. The port can still be accessed by a via, if the via is entirely inside the port. In Figure , the router can only access the metal1 port from the right. If the metal2 obstruction did not exist, the router could connect to the port with a metal12 via, as long as the metal1 part of the via fit entirely inside the metal1 port.

Routing can also connect to such a port on the same layer if the routing does not cross any obstruction by more than a distance of the total of minimum width plus minimum spacing before reaching the pin.

This is because the port geometry is known to be "real," and any obstruction less than a distance of minimum width plus minimum spacing away from the port is not a real obstruction. If the pin is more than minimum width plus minimum spacing away from the obstruction edge, the router can only route to the pin from the layer above or below using a via see Figure If a port is on the edge of the obstruction, a wire can be routed to the port without violations.

Pins that are partially covered with obstructions or in apparent violation with nearby obstructions can limit routing options. Even though the violations are not real, the router assumes they are.

In these cases, extend each obstruction to cover the pin. The router then accesses the pin as described above. Significant routing time can be saved if obstructions are simplified. Especially in metal1 , construct obstructions so that free tracks on the layer are accessible to the router.

If most of the routing resource is obstructed, simplify the obstruction modeling by combining small obstructions into a single large obstruction. For example, use the bounding box of all metal1 objects in the cell, rather than many small obstructions, as the bounding box of the obstruction. You must be sure to model via obstructions over the rest of the cell properly. A single, large cut12 obstruction over the rest of the cell can do this in some cases, as when metal1 resource exists within the cell outside the power buses.

Normally, footprint descriptions in LEF are rectangular. However, it is possible to describe rectilinear footprints using an overlap layer. The overlap layer is defined specifically for this purpose and does not contain any routing. Describe a rectilinear footprint by setting the SIZE of the macro as a whole to a rectangular bounding box, then defining obstructions within the bounding box on the overlap layer. The obstructions on the overlap layer indicate areas within the bounding box which no other macro should overlap.

The obstructions should completely cover the rectilinear shape of the macro, but not the portion of the bounding box that might overlap with other macros during placement. Note: Specify the overlaps for the macro using the OBS statement. The first pin listed becomes the first pin in the database. List the pins in the following order:. Example Pin Antenna Model.

The following example describes oxide model information for pins IN1 and IN2. Pin that drives signals out of the cell. Example Net Expression and Supply Sensitivity. The following statement defines sensitivity and net expression values for four pins on the macro myMac :. END myMac. PIN pinName. Specifies the port type. Default: NONE. BUMP --Specifies the port is a bump connection point.

CORE --Specifies the port is a core ring connection point. NONE --Specifies the port is a default port that is connected by normal "default" routing. Defines port geometries for the pin. You specify port geometries using layer geometries syntax. You can use the via in pin only rule to specify that vias must be dropped inside the original pin shapes to connect to the pin. You can create a via in pin only rule by using the following property definition:. Pin that goes straight through cells with a regular shape and connects to pins on adjoining cells without routing.

Pin on a large block that forms a ring around the block to allow connection to any point on the ring. Cover macro special pins also typically have shape RING. Figure shows an example of an abutment and a feedthrough pin. Note: When you define feedthrough and abutment pins for use with power routing, you must do the following:. Pin is used for connectivity to the chip-level ground distribution network. Pin is used for connectivity to the chip-level power distribution network.

Defines the manufacturing grid for the design. The manufacturing grid is used for geometry alignment. When specified, shapes and cells are placed in locations that snap to the manufacturing grid. Specifies the maximum number of single-cut stacked vias that are allowed on top of each other that is, in one continuous stack. A via is considered to be in a stack with another via if the cut of the first via overlaps any part of the cut of the second via.

A double-cut or larger via interrupts the stack. For example, a via stack consisting of single via12 , single via23 , double-cut via34 , and single via45 has a single-cut stack of height 2 for via12 and via23 , and a single-cut stack of height 1 for via45 because the full stack is broken up by double-cut via Example Maximum Via Stack Statement. This rule applies to all layers.

LAYER metal9. If you specify the following statement instead, the stacked via limit applies only to layers metal1 through metal7. Defines the wiring width, design rule spacing, and via size for regular signal nets. You do not need to define cut layers for the nondefault rule. Some tools have limits on the total number of nondefault rules they can store. This limit can be as low as 30; however most tools that support 90 nanometer rules that is, LEF 5.

Note: Use the VIA statement to define vias for nondefault wiring. END layerName. VIA viaStatement. Example Nondefault Rule Statement. END via12rule. END via23rule. Because there are none defined, the default via rules are implicitly inherited for this nondefault rule; therefore, via12rule and via23rule would be used for this routing rule.

END wide3x. Lists all properties used in the LEF file. RANGE min max. Example Property Definitions Statement. Defines a placement site in the design. Specifies a set of previously defined sites and their orientations that together form siteName.

Specifies the name of a previously defined site. The height of each previously defined site must be the same as the height specified for siteName , and the sum of the widths of the previously defined sites must equal the width specified for siteName. Specifies the orientation for the previously defined site. Example Site Row Pattern Statement.

The following example defines three sites: Fsite ; Lsite ; and mySite , which consists of a pattern of Fsite and Lsite sites:. SITE Fsite. END Fsite. SITE Lsite. END Lsite. SITE mySite. END mySite. Figure illustrates some DEF rows made up of mySite sites. SITE siteName. Specifies the dimensions of the site in normal or north orientation, in microns. Indicates which site orientations are equivalent. The sites in a given row all have the same orientation as the row.

Generally, site symmetry should be used to control the flipping allowed inside the rows. Site is symmetric about the x axis. A macro with an orientation of N matches N or FS rows. Site is symmetric about the y axis. A macro with an orientation of N matches N or FN rows. Site is symmetric about the x and y axis. Site is symmetric when rotated 90 degrees. Typically, this value is not used.

Note: Typically, a site for single-height standard cells uses symmetry Y , and a site for double-height standard cells uses symmetry X Y. Defines the units of measure in LEF. The values tell you how to interpret the numbers found in the LEF file. Units are fixed with a convertFactor for all unit types, except database units and capacitance. For more information, see "Convert Factors". Interprets one LEF distance unit as multiplied when converted into database units.

In this case, one micron would equal database units. Database precision is relative to Standard International SI units. LEF values are converted to integer values in the library database as follows. SI unit. Database precision. The following table illustrates the conversion of LEF distance units into database units. Database Units. Specifies technology name for design in data base.

Specifies database units per microns to convert DEF db units into microns. In this sections all the properties are listed. Information like object type component, pin, net, region, etc. Specifies the coordinates of die. In case of rectangle die four coordinates will be specified and if it is more means it represents a rectilinear die shape.

Coordinates unit will be as per specified in UNIT section. ROWS statement. Defines rows in the design. This section describes the routing grid of the design. VIAS statement. This section contains the list of via names and via geometry information used in design.

One can find via cut layer, cut size, bottom routing layer, top routing layer, via enclosure information, via offset from this section. Defines the convex polygon defined at the each endpoints of a wire. All the non default rules used in design, whether it is specified in LEF file or not, are stored in this section of DEF file. Any region specified in the design is described under this section. Saves region coordinates, its type and properties.

A region is a physical area in which group of cells are placed. All the physical attributes cell type, name, physical status, orientation, halo, region, etc. It includes macros as well as standard cells.

PINS section. Describes all IO ports in the design, their properties and antenna rules associated with each port. Specifies all pins for each component in design along with their attributes. Lists placement and routing blockages used in design and all the physical attributes associated with them. SLOTS section. If slots are created for wire shapes in the design then they are represented here in rectangular form.

FILLS section. Metal fills in the design are listed here. What is the definition of Thermal Design Power? Started by blaze Dec 22, Replies: 0. What is the definition of a leaf cell? Started by bradyue Oct 20, Replies: 6. What is the serious definition of a "BUS"? Started by sweesw Jul 18, Replies: 8. Part and Inventory Search. Welcome to EDABoard. This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register. By continuing to use this site, you are consenting to our use of cookies.